simplex
Link to the guide: https://cdrdv2-public.intel.com/703047/intel-gfx-prm-osrc-tgl-vol-02-c-command-reference-registers-part-2.pdf
On page 692 of the guide, it is stated that bits 5-7 of the register are the Dithering BPC bits, and the 4th bit is the Dithering Enable bit. This means that bits 5-7 set the color depth for dithering. According to my experiments, no matter what values I set for bits 5-7, there is no effect on the i5-12400 (UHD 730) as long as the 4th bit is zero, meaning dithering is off. However, if the 4th bit is set to one, enabling dithering, then bits 5-7 can be used to adjust dithering depth. But this is not what we need, as we actually want to get rid of dithering.
However, when attempting to change bits 5-7 for the Intel UHD 48EUs (i5-12450H), the color depth of the output signal changes, while the Dithering Enable bit (the 4th bit) remains set to zero. This behavior is different from the desktop i5-12400 iGPU.
However, I was led to these experiments after reading a comment in the Linux kernel in the i915 module. It stated:
For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with valid values of: 6, 8, 10 BPC.
ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: 6, 8, 10, 12 BPC.
I know that there is a way to switch to true 6-bit on the Alder Lake i5-12400, as the i915 module in Linux does this. However, in Linux, this is done through the convenient xrandr tool, and I'm not ready to say which other registers are involved in this process.